1. Field of the Invention
The present invention relates to a semiconductor device having a high breakdown voltage and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device having a high breakdown voltage for use in a high-voltage inverter or the like, and a method of manufacturing the same.
2. Description of the Background Art
Semiconductor devices having a high breakdown voltage for use in high-voltage inverters or the like have recently been demanded to have a higher operation speed and a lower on-voltage in order to improve an operation efficiency and an operation controllability of the high-voltage inverters. In a field of a class of thousands of volts, GTO (Gate Turn-Off) thyristors have been largely used. However, it has been recently studied to improve breakdown voltages of IGBTs (Insulated Gate Bipolar Transistors) which allow increase in speed of devices.
Works are now being made to develop IGBTs of a gate trench type which can increase a supply capacity of electrons by microscopic processing. However, achievement of high operation speed and low on-voltage unpreferably causes reduction in a breakdown voltage, and therefore it is necessary to improve limits for them.
Referring to FIG. 49, description will be given on a structure of an IGBT of a gate trench type having a high breakdown voltage which has been studied.
FIG. 49 is a schematic cross section of an IGBT of a gate trench type having a high breakdown voltage.
The gate trench type IGBT having a high breakdown voltage includes a lightly doped n.sup.- silicon substrate 1 and p-wells 4 which are formed of p-type impurity diffusion regions formed at a first main surface (upper surface in the figure) of n.sup.- silicon substrate 1. Gate trenches 70 extending from p-wells 4 into n.sup.- silicon substrate 1 are arranged with a certain pitch. Each gate trench 70 is formed of a gate trench groove 7a having a depth similar to the above pitch, a gate insulating film 7 arranged on an inner surface of gate trench groove 7a and a gate electrode 8 arranged inside gate insulating film 7.
At portions of p-wells 4 contiguous to first main surfaces of gate trenches 70, there are arranged n.sup.+ emitter regions 5 formed of heavily doped n-type impurity diffusion regions.
Portions of gate electrode 8 and gate insulating film 7 of each gate trench 70 which are protruded beyond the first main surface are covered with a silicate glass film 19. There is also formed an emitter electrode 10, which covers entirely the first main surface, is formed of, e.g., a metal film, and is electrically connected to n.sup.+ emitter regions 5 and p-wells 4.
An n-buffer layer 2 formed of an n.sup.+ impurity diffusion region is arranged at a second main surface (lower surface in the figure) of n.sup.- silicon substrate 1. A p-collector region 3 made of a p.sup.+ type impurity diffusion region is formed at a surface of n-buffer layer 2. A collector electrode 11 made of, e.g., a metal film is arranged at a surface of p-collector region 3. n-buffer layer 2 which is designed as a so-called punch through type is employed for improving a precision of the semiconductor device, and is not essential.
Operations of the above gate trench type IGBT having a high breakdown voltage will be described below.
First, an operation in an off state will be described below. A voltage is applied across collector electrode 11 and emitter electrode 10 while applying a voltage sufficiently lower than a gate threshold voltage across gate electrode 8 and emitter electrode 10. Thereby, a junction between n.sup.- silicon substrate 1 and p-well 4 attains a reversely biased state, and a depletion layer extends mainly toward n.sup.- silicon substrate 1. Since the gate potential is low, holes in p-well 4 are attracted to and accumulated at a surfaces of p-well 4 contiguous to gate trench 70, so that the gate trench channel attains an off state.
An operation in an on state will be described below. A voltage is applied across collector electrode 11 and emitter electrode 10 while applying a voltage sufficiently higher than the gate threshold voltage across gate electrode 7 and emitter electrode 10. Thereby, a surface contiguous to gate trench 70 attracts electrons in p-well 4, because the gate potential is high. Therefore, n-inversion occurs, and a trench channel is formed. Thereby, electrons in n.sup.- silicon substrate 1 are supplied from n.sup.+ emitter region 5 into n silicon substrate 1 through the trench channel, and electrons flow toward p-collector layer 3 carrying a positive potential.
When electrons flow into p-collector layer 3, holes are supplied from p-collector layer 3 into n-buffer layer 2. These holes cause conductivity modulation in n.sup.- silicon substrate 1. If a life time in n.sup.- silicon substrate 1 is sufficiently long, these holes reach the vicinity of the trench channel, and will be attracted into p-well 4 at a lower potential.
Description will now be given on a so-called turn-off state in which the state changes from on state to the off state described above. In an inverter circuit which is typical application of a switching element having a high breakdown voltage, an inductive load is controlled in many cases. FIG. 50 shows results of evaluation of the turn-off operation in a case where the inductive load is controlled in the conventional high-breakdown-voltage IGBT of the gate trench type.
When charges accumulated in the gate capacity decrease and the gate voltage lowers, a sufficient load current may not flow in the high-breakdown-voltage IGBT of the gate trench type, in which case a collector voltage rises. When the collector voltage exceeds 3000 V which is a bus voltage of the inverter circuit, the load current bypasses the IGBT and flows through a bus circuit, so that the collector current in the high-breakdown-voltage IGBT of the gate trench type decreases. When excessive carriers, which were accumulated in n.sup.- silicon substrate 1 and n-buffer layer 2 in the high-breakdown-voltage IGBT of the gate trench type during the on state, are discharged or released, the collector current of the high-breakdown-voltage IGBT of the gate trench type flows no longer, and the turn-off operation is completed.
The high-breakdown-voltage IGBT of the gate trench type described above suffers from the following problem in the off state. A current other than a slight leakage current generated inside a depletion layer does not flow between collector electrode 11 and emitter electrode 10, and a high impedance is exhibited.
With increase in collector voltage, the depletion layer further extends to n-buffer layer 2. The electric field in the IGBT increases as the voltage rises. Although the potential at the bottom of gate trench 70 is substantially equal to that at gate electrode 8, the potential, which n.sup.- silicon substrate 1 under p-well 4 carries at a position at the same depth as the bottom, rises above the potential at p-well 4 (emitter potential) due to donor ions between the above-mentioned position to p-well 4. In particular, the electric field at a bottom corner in gate trench 70 tends to increase.
In the above state, when the electric field inside the IGBT exceeds a threshold electric field and thereby tends to cause strong impact, a leakage current between collector electrode 11 and emitter electrode 10 rapidly increases, resulting in breakdown of the IGBT.
In order to achieve a high breakdown voltage of the IGBT, therefore, it is necessary to increase a drop voltage which exists in the depletion layer until the electric field reaches the threshold electric field. For this purpose, the thickness of n.sup.- silicon substrate 1 is increased so as to lower an impurity concentration. Also, in order weaken the electric field at the lower corner of gate trench 70 and thereby increase the threshold electric field, such a structure has been employed that the gate trench 70 has a round lower corner, or that a distance between gate trenches 70 is reduced (see the following reference 1).
Reference 1: K Matsushita, I Omura and T Ogura, "Blocking Voltage Design Consideration for Deep Trench MOS Gate High Power Devices" Proc., ISPSD' 95 pp. 256-260.
However, reduction in a distance between gate trenches 70 increases an area of gate trenches 70 per unit area, which unpreferably increases the gate capacity and provides a severe limit to processing for fabricating the IGBT.
Then, a problem during the on state will be described below.
A density of electrons and holes in n.sup.- silicon substrate 1 increases and a low impedance is attained between collector electrode 11 and emitter electrode 10. However, a relatively large number of holes are attracted into p-well 4. This restricts introduction of electrons from the trench channel into n.sup.- silicon substrate 1.
A conventional IGBT, which has been studied for a practical use, exhibits such a carrier density distribution that a carrier density near the collector electrode is higher than that near the emitter electrode as shown in FIG. 51.
The on-voltage can be lowered by strengthening the conductivity modulation of n.sup.- silicon substrate 1. The on-voltage lowers in accordance with increase in lifetime of carriers in n.sup.- silicon substrate 1, increase in supply of electrons from the trench channel side and increase in supply of holes from p-collector layer 3. Particularly in the IGBT of a class of thousands of volts, supply of an excessively large amount of holes from p-collector layer 3 causes a problem, so that such a design is required that electrons can be supplied from the trench channel side as much as possible.
In order to increase the supply of electrons from the trench channel side, it is necessary to reduce an amount of holes flowing into p-well 4. For achieving this, the following structures have been proposed in the prior art:
(i) Structure in which a pitch of gate trenches is reduced (see reference 2).
(ii) Structure in which gate trenches have a large depth (see reference 2).
(iii) Structure which corresponds to the structure of IGBT shown in FIG. 49 and includes a heavily doped n-type layer under p-well 4.
(iv) Structure in which an emitter contact of p-well 4 and a portion of gate trench 70 not provided with n-emitter region 5 are inserted between trench IGBT portions (see FIG. 50, and references 2 and 3).
Reference 2: M Kitagawa, A Nakagawa, K Matsushita, S Hasegawa, Y Inoue, A Yahata and H Takenaka "4500V IEGTs having Switching Characteristics Superior to GTO" Proc. ISPSD' 95, pp. 485-491.
Reference 3: Japanese Patent Laying-Open No. 7-50405 (1995).
However, if IGBTs were designed as described above, the structures of (i), (ii) and (iv) would suffer from a problem that increase in gate capacity, and the structures of (ii) and (iii) would suffer from a problem of lowering of breakdown voltages. The former problem is geometrically apparent from the fact that an area ratio of the gate insulating film is large. An example of the latter problem will be described below with reference to FIG. 53, which shows results of evaluation of breakdown voltages and saturation voltages in IGBTs of a class of 4500 volts with various heavily doped n-type layers formed at various depths under p-wells 4 and having different impurity concentrations. As structure parameters of the reference IGBT for the above evaluation, the impurity concentration of n.sup.- silicon substrate 1 is 1.3e13/cm.sup.3, a thickness is 625 .mu.m, a pitch of gate trenches 70 is 5 .mu.m and a depth thereof is 5 .mu.m.
As shown in FIG. 53, the saturation voltage is certainly lower than that of the reference IGBT (represented as reference TIGBT in the table). However, as the saturation voltage decreases to a higher extent, the breakdown voltage also decreases to a higher extent, so that it is impossible to find practically acceptable conditions of the impurity concentration and the position of the n-type layer.
A problem caused by the turn-off operation will be described below.
Referring again to FIG. 50, there is a range indicated by Z in the figure, in which the rapidly raised collector voltage (V.sub.CE) of about 1200 V rises slowly to about 3000 V. With reference to a cumulative waveform of a switching loss (E.sub.OFF) represented by broken line, a major portion of turn-on loss is consumed at the range indicated by Z.
As characteristics of IGBT shown in FIG. 50, there are shown waveforms of an element of which saturation voltage is set to about 3 V by controlling introduction of holes from p-collector layer 3. The structure parameters are as follows. The impurity concentration of silicon substrate is 1.0e13/cm.sup.3, a thickness is 425 .mu.m, a gate trench pitch is 5.3 .mu.m, a depth is 5 .mu.m and a width is 1 .mu.m.
The above phenomenon has been elucidated as follows by analyzing an internal state of the IGBT used for the device simulation. When carriers accumulated in the IGBT are discharged and the collector voltage rises, the depletion layer does not extend rapidly from the emitter electrode side if a large amount of carriers are accumulated at a neutral region of n.sup.- silicon substrate 1 near the collector electrode, so that the collector voltage rises slowly.
At the same time, the following phenomenon occurs. A difference in charge density between holes and electrons forming a current acts to modulate and therefore enhance the electric field in the depletion layer, and impact-generated carriers transitionally supply an electron current, which delays turn-off.
In order to suppress the above phenomenon for reducing the turn-off loss, it is necessary to employ a design which can avoid excessive accumulation of carriers at the neutral region in n.sup.- silicon substrate 1 near the collector electrode in the on state. However, mere suppression of introduction of holes from p-collector layer 3 would result in rise of the saturation voltage and therefore increase in the on-state loss.